Verification Challenge in 3D Integrated Circuits (IC) Design

Authors

Niranjana Gurushankar

Abstract

Three-dimensional integrated circuits (3D ICs) have emerged as a promising solution to overcome the limitations of traditional 2D ICs, offering improved performance, reduced power consumption, and increased functionality. However, the increased complexity introduced by stacking multiple dies vertically presents significant challenges for verification. Traditional verification methodologies are inadequate for 3D ICs due to the intricate interactions between stacked dies, including thermal effects, through-silicon vias (TSVs), and inter-die signaling. We delve into the complexities of verifying these interactions, focusing on the need for accurate modeling and simulation techniques. Furthermore, we discuss the challenges posed by increased design complexity and the need for efficient debugging and validation strategies. New approaches, such as formal verification, advanced simulation, and 3D-specific DFT strategies are needed. This paper provides a comprehensive overview of 3D IC verification challenges to guide future research and development.

Keywords

3D integrated circuits (3D ICs), Verification, Inter-die signaling, Electronic Design Automation (EDA) tools, Formal verification, Design-for-Testability (DFT), Machine learning, Fault prediction.

Verification Challenge in 3D Integrated Circuits (IC) Design. Niranjana Gurushankar. 2020. IJIRCT, Volume 6, Issue 1. Pages 1-6. https://www.ijirct.org/viewPaper.php?paperId=2412047